System-in-packages (SiPs) of various three-dimensional (3D) stacked architectures have found increasing use in the field of integrated circuit (IC) SiP testing. For example, a 3D SiP of the most typical type, i.e., an SiP containing two vertically stacked chips, can be formed by any of the following approaches:
1) three-dimensionally attaching the two vertically stacked dies onto a substrate with a curing adhesive, and connecting contacts of the two dies to the substrate with wire bonds;
2) three-dimensionally attaching the two vertically stacked dies onto a substrate with a curing adhesive, and using wire bonds to connect the contacts of the upper die to a bond pad of the lower die and the contacts of the lower die to the substrate;
3) flipping over the upper die, interconnecting the upper and lower dies by reflowing solder bumps that have been formed on surfaces of the upper and lower dies in advance, and connecting the contacts of the lower die to the substrate using wire bonds; and
4) flipping over the upper die, interconnecting the upper and lower dies by reflowing solder bumps that have been formed on surfaces of the upper and lower dies in advance, and connecting the contacts of the lower die to the substrate through preformed silicon vias (TSVs) extending between the contacts and a back side of the lower die.
In these approaches, the solder bump flip chip processes have been finding increasingly extensive use, particularly in the future high density SiPs based on TSVs and micro-solder-bump flip chip process. However, the application of the solder-bump flip chip process using densely arranged solder bumps in 3D stacking and interconnection still remains a great challenge and leads to high manufacturing costs. In particular, the void-free filling and reliable curing of a liquid medium within the gaps between the dies after the flipping and solder bump reflowing is a very challenging process to yield and cost issues.